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general description the max1446 10-bit, 3v analog-to-digital converter(adc) features a fully differential input, a pipelined 10- stage adc architecture with digital error correction and wideband track and hold (t/h) incorporating a fully dif- ferential signal path. this adc is optimized for low- power, high dynamic performance applications in imaging and digital communications. the max1446 operates from a single 2.7v to 3.6v supply, consuming only 90mw while delivering a 59.5db signal-to-noise ratio (snr) at a 20mhz input frequency. the fully differ- ential input stage has a 400mhz, -3db bandwidth and may be operated with single-ended inputs. in addition to low operating power, the max1446 features a 5? power-down mode for idle periods. an internal 2.048v precision bandgap reference is used to set the adc full-scale range. a flexible reference structure allows the user to supply a buffered, direct or externally derived reference for applications requiring increased accuracy or a different input voltage range. lower and higher speed, pin-compatible versions of the max1446 are also available. refer to the max1444 data sheet for a 40msps version, the max1448 data sheet for an 80msps version, and the max1449 data sheet for a 105msps version. the max1446 has parallel, offset binary, three-state outputs that can be operated from 1.7v to 3.3v to allow flexible interfacing. the device is available in a 5mm x 5mm, 32-pin tqfp package and is specified over the extended industrial (-40? to +85?) and automotive (-40? to +105?) temperature ranges. ________________________applications ultrasound imagingccd imaging baseband and if digitization digital set-top boxes video digitizing applications features ? single 3.0v operation ? excellent dynamic performance 59.5db snr at f in = 20mhz 73db sfdr at f in = 20mhz ? low power: 30ma (normal operation)5? (shutdown mode) ? fully differential analog input ? wide 2v p-p differential input voltage range ? 400mhz -3db input bandwidth ? on-chip 2.048v precision bandgap reference ? cmos-compatible three-state outputs ? 32-pin tqfp package ? evaluation kit available (max1448 ev kit) max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference ________________________________________________________________ maxim integrated products 1 clk in+ control 10 pipeline adc ref system + bias output drivers d e c ref refin refout refp com refn oe v dd gndov dd ognd d9?0 in- pd t/h max1446 functional diagram 19-1729; rev 4; 11/08 evaluation kit available ordering information part temp range pin-package max1446ehj+ -40? to +85? 32 tqfp MAX1446GHJ+ -40? to +105? 32 tqfp for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin-compatible, lower/higher speed versions part sampling speed (msps) max1444 40 max1448 80 max1449 105 + denotes a lead(pb)-free/rohs-compliant package. downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v dd = 3.0v, ov dd = 2.7v; 0.1? and 1.0? capacitors from refp, refn, and com to gnd; v refin = 2.048v, refout connected to refin through a 10k resistor, v in = 2v p-p (differential with respect to com), c l 10pf at digital outputs, f clk = 62.5mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd ...............................................-0.3v to +3.6v ognd to gnd.......................................................-0.3v to +0.3v in+, in- to gnd........................................................-0.3v to v dd refin, refout, refp, refn, and com to gnd.........................-0.3v to (v dd + 0.3v) oe , pd, clk to gnd..................................-0.3v to (v dd + 0.3v) d9?0 to gnd.........................................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70 c) 32-pin tqfp (derate 18.7mw/ c above +70 c)......1495.3mw operating temperature ranges: max1446ehj+ .................................................-40 c to +85 c MAX1446GHJ+...............................................-40 c to +105 c storage temperature range ............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl f in = 7.492mhz, t a +25? 0.6 1.9 lsb differential nonlinearity dnl no missing codes, f in = 7.492mhz 0.4 1.0 lsb offset error -1.6 < 0.1 1.9 % fs gain error t a +25? 0 2.0 % fs analog input input differential range v diff differential or single-ended inputs 1.0 v common-mode voltage range v com v dd /2 0.5 v input resistance r in switched capacitor load 33 k input capacitance c in 5p f conversion rate maximum clock frequency f clk 60 mhz data latency 5.5 cycles dynamic characteristics f in = 7.492mhz 57 59.5 f in = 19.943mhz 56.5 59.5 signal-to-noise ratio snr f in = 39.9mhz (note 1) 59 db f in = 7.492mhz 56.6 59.4 f in = 19.943mhz 56.2 59 signal-to-noise + distortion(up to 5th harmonic) sinad f in = 39.9mhz (note 1) 58.5 db f in = 7.492mhz 65 74 f in = 19.943mhz 63 73 spurious-free dynamicrange sfdr f in = 39.9mhz (note 1) 71 dbc downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference _______________________________________________________________________________________ 3 electrical characteristics (continued)(v dd = 3.0v, ov dd = 2.7v; 0.1? and 1.0? capacitors from refp, refn, and com to gnd; v refin = 2.048v, refout connected to refin through a 10k resistor, v in = 2v p-p (differential with respect to com), c l 10pf at digital outputs, f clk = 62.5mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units f in = 7.492mhz -74 f in = 19.943mhz -73 third-harmonic distortion hd3 f in = 39.9mhz (note 1) -71 dbc two-tone intermodulationdistortion imd tt f 1 = 19mhz at -6.5dbfs, f 2 = 21mhz at -6.5dbfs (note 2) -75 dbc third-order intermodulationdistortion im3 f 1 = 19mhz at -6.5dbfs f 2 = 21mhz at -6.5dbfs (note 2) -75 dbc f in = 7.492mhz -70 -64 f in = 19.943mhz -70 -63 total harmonic distortion(first 5 harmonics) thd f in = 39.9mhz (note 1) -69 dbc small-signal bandwidth input at -20dbfs, differential inputs 500 mhz full-power bandwidth fpbw input at -0.5dbfs, differential inputs 400 mhz aperture delay t ad 1n s aperture jitter t aj 2 psrms overdrive recovery time for 1.5 full-scale input 2 ns differential gain 1% differential phase 0.25 output noise in+ = in- = com 0.2 lsbrms internal reference reference output voltage refout 2.048 1% v reference temperaturecoefficient tc ref 60 ppm/ c load regulation 1.25 mv/ma buffered external reference (v refin = 2.048v) refin input voltage v refin 2.048 p osi ti ve refer ence outp ut v ol tag ev refp 2.012 v n eg ati ve refer ence outp ut v ol tag e v refn 0.988 v common-mode level v com v dd /2 v differential reference outputvoltage range v ref v ref = v refp - v refn , t a +25 c 0.98 1.024 1.07 v refin resistance r refin > 50 m maximum refp, com sourcecurrent i source 5m a maximum refp, com sinkcurrent i sink -250 ? downloaded from: http:///
parameter symbol conditions min typ max units maximum refn source current i source 250 ? maximum refn sink current i sink -5 ma unbuffered external reference (v refin = agnd, reference voltage applied to refp, refn, and com) refp, refn input resistance r refp , r refn measured between refp and com andrefn and com 4k refp, refn, com inputcapacitance c in 15 pf differential reference inputvoltage range v ref v ref = v refp - v refn 1.024 10% v com input voltage range v com v dd /2 10% v refp input voltage v refp v com + v ref /2 v refn input voltage v refn v com - v ref /2 v digital outputs (clk, pd, oe ) clk 0.8 x v dd input high threshold v ih pd, oe 0.8 x ov d d v clk 0.2 x v dd input low threshold v il pd, oe 0.2 x ov d d v input hysteresis v hyst 0.1 v i ih v ih = v dd = ov dd 5 input leakage i il v il = 0 5 ? input capacitance c in 5p f digital outputs (d9?0) output voltage low v ol i sink = 200? 0.2 v output voltage high v oh i source = 200? ov dd - 0.2 v three-state leakage current i leak oe = ov dd 10 ? three-state output capacitance c out oe = ov dd 5p f max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference 4 _______________________________________________________________________________________ electrical characteristics (continued)(v dd = 3.0v, ov dd = 2.7v; 0.1? and 1.0? capacitors from refp, refn, and com to gnd; v refin = 2.048v, refout connected to refin through a 10k resistor, v in = 2v p-p (differential with respect to com), c l 10pf at digital outputs, f clk = 62.5mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25 c.) downloaded from: http:///
max1446 note 1: snr, sinad, thd, sfdr, and hd3 are based on an analog input voltage of -0.5dbfs referenced to a 1.024v full-scaleinput voltage range. note 2: intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. this number i s 6db better, if referenced to the two-tone envelope. note 3: digital outputs settle to v ih , v il . note 4: wake-up time is defined as the time from complete reference power-down until the adc performs within 0.3 enob of thefinal performance for f in = 10mhz at -0.5dbfs input amplitude. v refin = 2.048v, refp, refn, and cml decoupled with 2.3?. note 5: dynamic characteristics guaranteed at f in = 19.943mhz for the specified duty-cycle range. note 6: guaranteed by design and engineering characterization. 10-bit, 60msps, 3.0v, low-power adc with internal reference _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units power requirements analog supply voltage v dd 2.7 3.0 3.6 v output supply voltage ov dd c l = 10pf 1.7 3.0 3.6 v operating, f in = 19.943mhz at -0.5dbfs 30 37 ma analog supply current i vdd shutdown, clock idle, pd = oe = ov dd 41 5 a operating, c l = 15pf, f in = 19.943mhz at -0.5dbfs 7m a output supply current i ovdd shutdown, clock idle, pd = oe = ov dd 12 0 a offset 0.1 mv/v power-supply rejection psrr gain 0.1 %/v timing characteristics clk rise to output data valid t do figure 5 (notes 3, 6) 2 5 8 ns oe fall to output enable t enable figure 5 10 ns oe rise to output disable t disable figure 5 1.5 ns clock duty cycle figure 6, clock period 16ns (notes 5, 6) 45 55 % wake-up time t wake (notes 4, 6) 366 520 ? electrical characteristics (continued)(v dd = 3.0v, ov dd = 2.7v; 0.1? and 1.0? capacitors from refp, refn, and com to gnd; v refin = 2.048v, refout connected to refin through a 10k resistor, v in = 2v p-p (differential with respect to com), c l 10pf at digital outputs, f clk = 62.5mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25 c.) downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference 6 _______________________________________________________________________________________ typical operating characteristics (v dd = 3.0v, ov dd = 2.7v, internal reference, differential input at -0.5dbfs, f clk = 62.35mhz, c l 10pf, t a = +25?, unless otherwise noted.) max1446 toc01 -100 -70-80 -90 -50-60 -10-20 -30 -40 0 0 5 10 15 20 25 30 35 fft plot (f in = 7.5mhz, 8192-point fft, differential input) analog input frequency (mhz) amplitude (db) sfdr = 72.2dbcsnr = 60.1db thd = -71.5dbc sinad = 59.8db hd2 hd3 -100 -70-80 -90 -50-60 -10-20 -30 -40 0 0 5 10 15 20 25 30 35 fft plot (f in = 13.3mhz, 8 192-point fft, differential input) max1446 toc02 analog input frequency (mhz) amplitude (db) sinad = 59.3dbsnr = 59.5db thd = -72.9dbc sfdr = 74.3dbc hd2 hd3 -100 -70-80 -90 -50-60 -10-20 -30 -40 0 0 5 10 15 20 25 30 35 fft plot (f in = 20mhz, 8192-point fft, differential input) max1446 toc03 analog input frequency (mhz) amplitude (db) sinad = 59.3dbsnr = 59.6db thd = -70.7dbc sfdr = 72.2dbc hd2 hd3 -100 -70-80 -90 -50-60 -10-20 -30 -40 0 0 5 10 15 20 25 30 35 fft plot (f in = 26. 8 mhz, 8 192-point fft, differential input) max1446 toc04 analog input frequency (mhz) amplitude (db) sinad = 59.0dbsnr = 59.4db thd = -70.5dbc sfdr = 72.9dbc hd2 hd3 -100 -70-80 -90 -50-60 -10-20 -30 -40 0 0 5 10 15 20 25 30 35 fft plot (f in = 50mhz, 8 192-point fft, differential input) max1446 toc05 analog input frequency (mhz) amplitude (db) sfdr = 70dbcsnr = 59.1db thd = -67.1dbc sinad = 58.5db hd2 hd3 -100 -70-80 -90 -50-60 -10-20 -30 -40 0 0 5 10 15 20 25 30 35 fft plot (f in = 7.5mhz, 8 192-point fft, single-ended input) max1446 toc06 analog input frequency (mhz) amplitude (db) sinad = 59.5dbsnr = 59.7db thd = -73.0dbc sfdr = 73.6dbc hd2 hd3 -100 -70-80 -90 -50-60 -10-20 -30 -40 0 0 5 10 15 20 25 30 35 fft plot (f in = 20mhz, 8 192-point fft, single-ended input) max1446 toc07 analog input frequency (mhz) amplitude (db) sinad = 59.2dbsnr = 59.5db thd = -70.7dbc sfdr = 71.1dbc hd2 hd3 -100 -70-80 -90 -50-60 -10-20 -30 -40 0 0 5 10 15 20 25 30 35 two-tone intermodulation ( 8 192-point imd, differential input) max1446 toc08 analog input frequency (mhz) amplitude (db) f 1 = 19mhz at -6.5dbfs f 2 = 21mhz at -6.5dbfs 3rd imd = -76dbc spurious-free dynamic range vs. analog input frequency (a in = -0.5dbfs) analog input frequency (mhz) sfdr (dbc) max1446 toc09 0 102030405060708090 50 55 60 65 70 75 80 differential single-ended downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.7v, internal reference, differential input at -0.5dbfs, f clk = 62.35mhz, c l 10pf, t a = +25?, unless otherwise noted.) spurious-free dynamic range vs. temperature temperature ( c) sfdr (dbc) max1446 toc17 -40 -15 10 35 60 85 60 64 68 72 76 80 f in = 19.943mhz, a in = -0.5dbfs signal-to-noise ratio vs. temperature temperature ( c) snr (db) max1446 toc18 -40 -15 10 35 60 85 50 54 58 62 66 70 f in = 19.943mhz, a in = -0.5dbfs signal-to-noise ratio vs. analog input frequency (a in = -0.5dbfs) analog input frequency (mhz) snr (db) max1446 toc10 0 102030405060708090 55 56 57 58 59 60 differential single-ended total harmonic distortion vs. analog input frequency (a in = -0.5dbfs) analog input frequency (mhz) thd (dbc) max1446 toc11 0 102030405060708090 -80 -75 -70 -65 -60 -55 -50 differential single-ended signal-to-noise and distortion vs. analog input frequency (a in = -0.5dbfs) analog input frequency (mhz) sinad (db) max1446 toc12 0 102030405060708090 52 53 54 55 56 57 58 59 60 differential single-ended spurious-free dynamic range vs. analog input power (f in = 19.943mhz) analog input power (dbfs) sfdr (dbc) max1446 toc13 -20 -16 -12 -8 -4 0 50 55 60 65 70 75 80 signal-to-noise ratio vs. analog input power (f in = 19.943mhz) analog input power (dbfs) snr (db) max1446 toc14 -20 -16 -12 -8 -4 0 30 36 42 48 54 60 66 total harmonic distortion vs. analog input power (f in = 19.943mhz) analog input power (dbfs) thd (dbc) max1446 toc15 -20 -16 -12 -8 -4 0 -80 -75 -70 -65 -60 -55 -50 signal-to-noise and distortion vs. analog input power (f in = 19.943mhz) analog input power (dbfs) sinad (db) max1446 toc16 -20 -16 -12 -8 -4 0 30 35 40 45 50 55 60 65 downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.7v, internal reference, differential input at -0.5dbfs, f clk = 62.35mhz, c l 10pf, t a = +25?, unless otherwise noted.) total harmonic distortion vs. temperature temperature ( c) thd (dbc) max1446 toc19 -40 -15 10 35 60 85 110 -80 -76 -72 -68 -64 -60 f in = 19.943mhz, a in = -0.5dbfs t a = +105 c signal-to-noise and distortion vs. temperature temperature ( c) sinad (db) max1446 toc20 -40 -15 10 35 60 85 110 50 54 58 62 66 70 f in = 19.943mhz, a in = -0.5dbfs t a = +105 c -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 400 200 600 800 1000 1200 integral nonlinearity vs. digital output code (best straight line) max1446 toc21 digital output code inl (lsb) f in = 7.5mhz -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0 400 200 600 800 1000 1200 differential nonlinearity vs. digital output code max1446 toc22 digital output code dnl (lsb) f in = 7.5mhz offset error vs. temperature, external reference (v refin = 2.04 8 v) temperature ( c) offset error (%fs) max1446 toc24 -40 -15 10 35 60 85 110 -10 -8 -6 -4 -2 0 2 4 6 8 10 t a = +105 c 2725 3129 33 35 2.70 3.00 2.85 3.15 3.30 3.45 3.60 analog supply current vs. analog supply voltage max1446 toc25 v dd (v) i vdd (ma) gain error vs. temperature, external reference (v refin = 2.04 8 v) temperature ( c) gain error (%fs) max1446 toc23 -40 -15 10 35 60 85 110 -10 -8 -6 -4 -2 0 2 4 6 8 10 t a = +105 c analog supply current vs. temperature temperature ( c) i vdd (ma) max1446 toc26 -40 -15 10 35 60 85 110 10 14 18 22 26 30 34 38 42 46 50 t a = +105 c 43 2 65 7 8 1.2 2.4 1.8 3.0 3.6 digital supply current vs. digital supply voltage max1446 toc27 ov dd (v) i ovdd (ma) f in = 7.5mhz downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v dd = 3.0v, ov dd = 2.7v, internal reference, differential input at -0.5dbfs, f clk = 62.35mhz, c l 10pf, t a = +25?, unless otherwise noted.) digital supply current vs. temperature temperature ( c) i ovdd (ma) max1446 toc28 -40 -15 10 35 60 85 110 0 4 8 12 16 20 f in = 7.5mhz t a = +105 c 3.02.5 2.0 4.03.5 4.5 5.0 2.70 3.00 2.85 3.15 3.30 3.45 3.60 analog power-down current vs. analog power supply max1446 toc29 v dd (v) i vdd ( a) oe = ov dd , pd = v dd 20 64 8 10 1.2 1.8 2.4 3.0 3.6 digital power-down current vs. digital power supply max1446 toc30 ov dd (v) i ovdd ( a) pd = v dd , oe = ov dd snr/sinad, -thd/sfdr vs. clock frequency clock frequency (mhz) snr/sinad, -thd/sfdr (db, dbc) max1446 toc31 50 54 58 62 66 70 50 56 62 68 74 80 sinad snr sfdr -thd f in = 20mhz, a in = -0.5dbfs 2.022.00 2.062.04 2.08 2.10 2.70 2.85 3.00 3.15 3.30 3.45 3.60 internal reference voltage vs. analog supply voltage max1446 toc32 v dd (v) v refout (v) internal reference voltage vs. temperature temperature ( c) v refout (v) max1446 toc33 -40 -15 10 35 60 85 110 2.00 2.02 2.04 2.06 2.08 2.10 t a = +105 c 0 20000 40000 60000 80000 100000 120000 140000 160000 n-2 n-1 n n+1 n+2 09 2 6 129421 725 0 output noise histogram (dc input) max1446 toc34 digital output code count downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference 10 ______________________________________________________________________________________ pin description pin name function 1 refn lower reference. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1? capacitor. 2 com common-mode voltage output. bypass to gnd with a > 0.1? capacitor. 3, 9, 10 v dd analog supply voltage. bypass to gnd with a capacitor combination of 2.2? in parallelwith 0.1?. 4, 5, 8, 11, 14, 30 gnd analog ground 6 in+ positive analog input. for single-ended operation, connect signal source to in+. 7 in- negative analog input. for single-ended operation, connect in- to com. 12 clk conversion clock input 13 pd power-down inputhigh: power-down mode low: normal operation 15 oe output enable inputhigh: digital outputs disabled low: digital outputs enabled 16?0 d9?5 three-state digital outputs d9?5. d9 is the msb. 21 ov dd output driver supply voltage. bypass to gnd with a capacitor combination of 2.2? inparallel with 0.1?. 22 t.p. test point. do not connect. 23 ognd output driver ground 24?8 d4?0 three-state digital outputs d4?0. d0 is the lsb. 29 refout internal reference voltage output. may be connected to refin through a resistor or aresistor-divider. 31 refin reference input. v refin = 2 (v refp - v refn ). bypass to gnd with a > 0.01? capacitor. 32 refp upper reference. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1? capacitor. downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 11 detailed description the max1446 uses a 10-stage, fully differential,pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. each sample moves through a pipeline stage every half-clock cycle. counting the delay through the output latch, the clock-cycle latency is 5.5. a 1.5-bit (2-comparator) flash adc converts the held input voltage into a digital code. the following digital- to-analog converter (dac) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. the resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been process- ed by all 10 stages. each stage provides a 1-bit resolu- tion. digital error correction compensates for adc comparator offsets in each pipeline stage and ensures no missing codes. input track-and-hold circuit figure 2 displays a simplified functional diagram of theinput t/h circuit in both track and hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuit samples the input signal onto the two capacitors (c2a and c2b). s2a and s2b set the common mode for the amplifier input. the resulting differential voltage is held on c2aand c2b. s4a, s4b, s5a, s5b, s1, s2a, and s2b are then opened before s3a, s3b and s4c are closed, con- necting capacitors c1a and c1b to the amplifier output, and s4c is closed. this charges c1a and c1b to the same values originally held on c2a and c2b. this value is then presented to the first stage quantizer and iso- lates the pipeline from the fast-changing input. the wide-input-bandwidth t/h amplifier allows the max1446 to track and sample/hold analog inputs of high frequencies beyond nyquist. the analog inputs (in+ and in-) can be driven either differentially or single ended. it is recommended to match the impedance of in+ and in- and set the common-mode voltage to mid- supply (v dd /2) for optimum performance. analog input and reference configuration the max1446 full-scale range is determined by theinternally generated voltage difference between refp (v dd /2 + v refin /4) and refn (v dd /2 - v refin /4). the adc? full-scale range is user adjustable through therefin pin, which provides a high input impedance for this purpose. refout, refp, com (v dd /2), and refn are internally buffered, low-impedance outputs. t/h v out x2 flash adc dac 1.5 bits mdac 10 v in v in stage 1 stage 2 d9?0 v in = input voltage between in+ and in- (differential or single ended) digital correction logic stage 10 figure 1. pipelined architecture?tage blocks s3b s3a com s5b s2b s5a in+in- s1 outout c2ac2b s4c s4a s4b c1b c1a internal bias internal bias com track track clk internalnonoverlapping clock signals hold hold s2a figure 2. internal t/h circuit downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference 12 ______________________________________________________________________________________ the max1446 provides three modes of reference oper-ation: internal reference mode buffered external reference mode unbuffered external reference mode in internal reference mode, the internal reference out- put (refout) can be tied to the refin pin through a resistor (e.g., 10k ) or resistor-divider if an application requires a reduced full-scale range. for stability pur-poses, it is recommended to bypass refin with a > 10nf capacitor to gnd. in buffered external reference mode, the reference volt- age levels can be adjusted externally by applying a stable and accurate voltage at refin. in this mode, refout may be left open or connected to refin through a > 10k resistor. in unbuffered external reference mode, refin is con-nected to gnd, thereby deactivating the on-chip buffers of refp, com, and refn. with their buffers shut down, these pins become high impedance and can be driven by external reference sources. clock input (clk) the max1446 clk input accepts cmos-compatibleclock signals. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). in particular, sampling occurs on the falling edge of the clock signal, mandating this edge to provide lowest possible jitter. any significant aperture jitter would limit the snr per- formance of the adc as follows: where f in represents the analog input frequency, and t aj is the time of the aperture jitter. clock jitter is especially critical for undersamplingapplications. the clock input should always be consid- ered as an analog input and routed away from any ana- log input or other digital signal lines. the max1446 clock input operates with a voltage threshold set to v dd /2. clock inputs with a duty cycle other than 50% must meet the specifications for highand low periods as stated in the electrical character- istics . see figures 3a, 3b, 4a, and 4b for the relation- ship between spurious-free dynamic range (sfdr),signal-to-noise ratio (snr), total harmonic distortion (thd), or signal-to-noise plus distortion (sinad) vs. duty cycle. output enable ( oe ), power-down (pd), and output data (d0?9) all data outputs, d0 (lsb) through d9 (msb), arettl/cmos-logic compatible. there is a 5.5 clock-cycle latency between any particular sample and its valid output data. the output coding is straight offset binary (table 1). with oe and pd (power-down) high, the digi- tal output enters a high-impedance state. if oe is held low with pd high, the outputs are latched at the lastvalue prior to the power-down. the capacitive load on the digital outputs d0?9 should be kept as low as possible (< 15pf) to avoid large digital currents that could feed back into the ana- log portion of the max1446, degrading its dynamic per- formance. the use of buffers on the adc? digital outputs can further isolate the digital outputs from heavy capacitive loads. to further improve the dynamic performance of the max1446 small series resistors (e.g., 100 ) may be added to the digital output paths, close to the adc.figure 5 displays the timing relationship between out- put enable and data output valid, as well as power- down/wake-up and data output valid. system timing requirements figure 6 shows the relationship between the clockinput, analog input, and data output. the max1446 snr ft in aj = ? ? ? ? ? ? 20 1 2 log table 1. max1446 output code for differential inputs differential input voltage* differential input straight offset binary v ref 511/512 +full scale -1lsb 11 1111 1111 v ref 510/512 +full scale -2lsb 11 1111 1110 v ref 1/512 +1lsb 10 0000 0001 0 bipolar zero 10 0000 0000 - v ref 1/512 -1lsb 01 1111 1111 - v ref 511/512 negative full scale + 1lsb 00 0000 0001 - v ref 512/512 negative full scale 00 0000 0000 *v refin = v refp = v refn downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 13 8070 60 50 40 20 40 30 50 60 70 clock duty cycle (%) sfdr (dbc) f in = 12.5mhz at -0.5dbfs figure 3a. sfdr vs. clock duty cycle (differential input) 40 5045 6055 65 70 20 40 30 50 60 70 clock duty cycle (%) snr (db) f in = 12.5mhz at -0.5dbfs figure 3b. snr vs. clock duty cycle (differential input) -40-50 -60 -70 -80 20 40 30 50 60 70 clock duty cycle (%) thd (dbc) f in = 12.5mhz at -0.5dbfs figure 4a. thd vs. clock duty cycle (differential input) 40 5045 6055 65 70 20 40 30 50 60 70 clock duty cycle (%) sinad (db) f in = 12.5mhz at -0.5dbfs figure 4b. sinad vs. clock duty cycle (differential input) output data d9?0 oe t disable t enable high-z high-z valid data figure 5. output enable timing downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference 14 ______________________________________________________________________________________ samples at the falling edge of the input clock. outputdata is valid on the rising edge of the input clock. the output data has an internal latency of 5.5 clock cycles. figure 6 also shows the relationship between the input clock parameters and the valid output data. applications information figure 7 shows a typical application circuit containing asingle-ended to differential converter. the internal refer- ence provides a v dd /2 output voltage for level shifting purposes. the input is buffered and then split to a volt-age follower and inverter. a lowpass filter follows the op amps to suppress some of the wideband noise associ- ated with high-speed op amps. the user may select the r iso and c in values to optimize the filter performance to suit a particular application. for the application infigure 7, an r iso of 50 is placed before the capaci- tive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small bypassing capacitor. using transformer coupling an rf transformer (figure 8) provides an excellentsolution for converting a single-ended source signal to a fully differential signal, required by the max1446 for optimum performance. connecting the transformer? center tap to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, may also improve the over-all distortion. in general, the max1446 provides better sfdr and thd with fully differential input signals than single- ended drive, especially for very high input frequencies. in differential input mode, even-order harmonics are lower since both inputs (in+, in-) are balanced, and each of the inputs only requires half the signal swing compared to single-ended mode. single-ended ac-coupled input signal figure 9 shows an ac-coupled, single-ended applica-tion. the max4108 op amp provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. buffered external reference drives multiple adcs multiple-converter systems based on the max1446 arewell suited for use with a common reference voltage. the refin pin of those converters can be connected directly to an external reference source. a precision bandgap reference like the max6062 generates an external dc level of 2.048v (figure 10), and exhibits a noise voltage density of 150n hz . its output passes through a 1-pole lowpass filter (with 10hz cutoff fre-quency) to the max4250, which buffers the reference before its output is applied to a second 10hz lowpass n - 6 n n - 5 n + 1 n - 4 n + 2 n - 3 n + 3 n - 2 n + 4 n - 1 n + 5 n n + 6 n + 1 5.5 clock-cycle latency analog inputclock input data output t do figure 6. system and output timing diagram downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 15 input 300 -5v 5v 0.1 f 0.1 f 0.1 f c in 22pf c in 22pf r iso 50 r iso 50 -5v 600 300 300 in+in- lowpass filter com 600 5v -5v 0.1 f 600 300 600 300 0.1 f 0.1 f 0.1 f 5v 0.1 f 300 max4108 max1446 max4108 max4108 lowpass filter figure 7. typical application circuit for single-ended to differential conversion max1446 t1 n.c. v in 4 3 2 5 6 1 22pf 22pf 0.1 f 0.1 f 2.2 f 25 25 mini-circuits adt1?wt in- in+ com figure 8. using a transformer for ac-coupling max1446 0.1 f 1k 1k 100 100 c in com c in in+in- 0.1 f r iso r iso refp refn r iso = 50 c in = 22pf v in max4108 figure 9. single-ended ac-coupled input downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference 16 ______________________________________________________________________________________ filter. the max4250 provides a low offset voltage (forhigh-gain accuracy) and a low noise level. the passive 10hz filter following the buffer attenuates noise pro- duced in the voltage reference and buffer stages. this filtered noise density, which decreases for higher fre- quencies, meets the noise levels specified for precision adc operation. unbuffered external reference drives multiple adcs connecting each refin to analog ground disables theinternal reference of each device, allowing the internal reference ladders to be driven directly by a set of exter- nal reference sources. followed by a 10hz lowpass fil- ter and precision voltage-divider (figure 11), the max6066 generates a dc level of 2.500v. the buffered outputs of this divider are set to 2.0v, 1.5v, and 1.0v, with an accuracy that depends on the tolerance of the divider resistors. the three voltages are buffered by the max4252, which provides low noise and low dc offset.the individual voltage followers are connected to 10hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3n hz . the 2.0v and 1.0v reference voltages set the differential full-scalerange of the associated adcs at 2v p-p . the 2.0v and 1.0v buffers drive the adc? internal ladder resistancesbetween them. note that the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. with the outputs of the max4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 adcs. for applications that require more than 32 matched adcs, a voltage reference and divider string common to all converters is highly recommended. refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 0.1 f 2.048v 100 f 2 5 3 2 3 1 4 1 max1446 n = 1 max4250 refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 0.1 f max1446 n = 1000 0.1 f 162 16.2k 3.3v 1 f 10hz lowpass filter 10hz lowpass filter note: one front-end reference circuit design may be used with up to 1000 adcs. 2.2 f 10v 0.1 f 0.1 f 3.3v max6062 figure 10. buffered external reference drives up to 1000 adcs downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 17 grounding, bypassing, __________________and board layout the max1446 requires high-speed board layout designtechniques. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface-mount devices for minimum inductance. bypass v dd , refp, refn, and com with two parallel 0.1? ceramic capacitors and a 2.2?bipolar capacitor to gnd. follow the same rules to bypass the digital supply (ov dd ) to ognd. multilayer boards with separated ground and power planes pro- duce the highest level of signal integrity. considerusing a split ground plane arranged to match the physi- cal location of the analog ground (gnd) and the digital output driver ground (ognd) on the adc's package. the two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. the ideal loca- tion of this connection can be determined experimen- tally at a point along the gap between the two ground planes that produces optimum results. make this con- nection with a low-value, surface-mount resistor (1 to 5 ), a ferrite bead, or a direct short. alternatively, all refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f 330 f 6v 330 f 6v 330 f 6v 10 f 6v 11 4 3 2 3 1 2 1 max1446 n = 1 max6066 1/4 max4252 refout 29 n.c. refin 31 refp 32 refn 1 com 2 0.1 f 0.1 f 0.1 f max1446 n = 32 47 2.0v at 8ma 1.47k 21.5k 3.3v 1 f 21.5k 21.5k 21.5k 21.5k note: one front-end reference circuit design may be used with up to 32 adcs. 2.2 f 10v 0.1 f 0.1 f 3.3v 2.0v 10 f 6v 11 4 5 6 7 1/4 max4252 47 1.5v at 0ma 1.47k 3.3v 10 f 6v 11 4 10 9 8 1/4 max4252 47 1.0v at -8ma 1.47k 3.3v 3.3v max4254 power-supply bypassing.place capacitor as close as possible to the op amp. 0.1 f 1.5v 1.0v figure 11. unbuffered external reference drives up to 32 adcs downloaded from: http:///
hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 12. t/h aperture timing max1446 ground pins could share the same ground plane if theground plane is sufficiently isolated from any noisy, dig- ital systems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensitive analog traces. keep all signal lines short and free of 90 turns. static parameter definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the valueson an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. the max1446? static linearity parameters are measured using the best-straight-line fit method. differential nonlinearity differential nonlinearity (dnl) is the difference betweenan actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. dynamic parameter definitions aperture jitter figure 12 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant whenan actual sample is taken (figure 12). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digitalsamples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum a/d noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr (max) = 6.02 x n + 1.76 in reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms sig- nal to the rms noise, which includes all spectral compo- nents minus the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms signalto all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc ata specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob is computed from: total harmonic distortion (thd) thd is typically the ratio of the rms sum of the inputsignal? first four harmonics to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rmsamplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious com- ponent, excluding dc offset. intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels ofeither input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -6.5db full scale. thd vvvv v = +++ ? ? ? ? ? ? ? ? 20 1 2345 2222 log enob sinad = (. ) . 176 602 10-bit, 60msps, 3.0v, low-power adc with internal reference 18 ______________________________________________________________________________________ downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference ______________________________________________________________________________________ 19 pin configurations (continued) max1446 tqfp top view 32 28 29 30 31 25 26 27 refingnd refout d0 refpd1 d2 d3 10 13 15 14 16 11 12 9 v dd gnd v dd pd clk oe gnd d9 17 18 19 20 21 22 23 ognd 24 d4t.p. ov dd d5d6 d7 d8 2 3 4 5 6 7 8 gnd in- in+ gnd gnd v dd com 1 refn package type package code document no. 32 tqfp h32-2f 21-0110 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . downloaded from: http:///
max1446 10-bit, 60msps, 3.0v, low-power adc with internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 11/07 various corrections; updated to extended temperature range for automotive applications; replaced tocs 9?0, 23, 24, 26, 30, 31, 33; updated package outlines. 1?, 15, 18, 20, 21 4 11/08 updates to the electrical characteristics table and notes section. 5, 14 downloaded from: http:///

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